Latest resources from Lattice Semiconductor Corporation
Pre-tested System-on-Chip Design Accelerates ...
Many moderate size Programmable Logic Device (PLD) designs, especially those in control plane applications, consist of a number of interfaces inter...
PRACTICAL LOW POWER CPLD DESIGN
Any engineer involved with portable or handheld products knows that minimizing power consumption is an absolute requirement for today's designs. Bu...
Implementing High-Speed DDR3 Memory Controlle...
Implementing a highspeed, high-efficiency DDR3 memory controller in a FPGA is a formidable task. Until recently, only a few high-end (read: expensi...
